Welcome to BitWise Blog!
SystemVerilog Functions vs Tasks
Stop Memorizing Syntax. Start Modeling Intent. When it comes to understanding SystemVerilog...
Practical UVM Factory
What You Actually Use Every Day If you read most explanations of the UVM factory, they begin with...
Know Your Configuration (UVM’s – KYC)
Introduction As UVM testbenches evolve from simple setups to complex, multi-layered environments,...
SystemVerilog Macros: Benefits, Pitfalls, and Best Practices
In SystemVerilog, macros provide a way to define reusable piece of code that can be inserted...
Beyond Functional Coverage: The Metric Analyzer
Introduction In ASIC verification, we all use a method known as Metric Driven Verification but we...
UVM Analysis Communication – Behind the scenes
Introduction We all know the importance of Transaction Level Modelling also known as TLM in UVM....
Only One is Needed, No More, No Less: The Singleton
Introduction: Design patterns In object oriented programming, we constantly create classes and...
Natural Selection and Coverage: Can Heuristic Algorithms Improve Test Bench Coverage?
In the realm of verification, coverage is essential in ensuring the closure on the functionality...